Based on Yusynth Quadrature VC-LFO
(which seems to be an adaptation of a state variable filter)

**Frequency range:** 19 Hz - 0.0008 Hz (20 min)

**Amplitude:** +-5V (10Vpp)

**Power draw:** +30mA, -27mA (depends on used LEDs)

**Startup stabilisation:** < 13 sec

Please copy, modify and let me know about your results.

youtube.com/watch?v=A-SHyvcifvg

Only 7 phases because I want it to be as small as possible (3HP)

The 8th phase (315°) can still be obtained by inverting the 4th output (135°).

**Eagle:** heptaphasis.sch, heptaphasis.brd (not the final version yet)

C9, C11 | 0805 470nF | integrator feedback, must be matched to within 1% or better. Lower value = faster oscillations. |

C12, C14, C15, C16, C17, C18, C19, C21, C22, C24, C25, C26, C27 | 0805 100nF | power filtration, value not critically important |

C3, C4, C5, C6, C7, C8, C23 | 0805 1nF | stabilisation caps, value not critically important, but higher values will introduce constant phase shift (1nF = 0.1ms, 10nF = 1ms) and filter out lower frequencies. Will work even if not installed. |

C10 | 0805 22pF | |

C20 | 0805 100nF | for startup amplitude circuit |

C1, C2 | THT 10µF electrolytic | 2mm lead pitch, <5mm diameter. Power filtration: 10µF or more. |

C13 | THT 10µF electrolytic | 2mm lead pitch, <5mm diameter. Higher value=longer increased frequency at startup |

T2, T3, T5, T6, T7, T8, T9 | SOT23 NPN | led driver, for example BC847 |

T1 | SOT23 NPN | eg. BC847 |

T4 | SOT23 PNP | eg. BC857 |

BCM857 | SOT-457-6 matched PNP pair | for example |

IC1, IC3 | SOIC14 TL074 | op amp |

IC2 | SOIC8 TL072 | op amp |

IC4 | SOIC16 LM13700 or NJM13700 | OTA |

R29, R34, R37, R41, R45, R49, R53 | 0805 470Ω-2kΩ | LED current limiting, choose according to desired LED brightness |

R30, R35, R38, R41, R48, R51, R55 | 0805 1kΩ | Output buffer protection |

R31, R36, R40, R43, R47, R52, R54 | 0805 330kΩ | LED driver gate. Too low value will distort the output waveform |

R3, R4 | 0805 ~68kΩ | summing resistors - value not too critical, but the pairs must be matched. The summing gain should be adjusted with TR2 and TR3 respectively |

R5, R6 | ||

R8, R44 | 0805 ~100kΩ | primary inverting buffers - values not critical, gain should be adjusted with TR1 and TR4 |

R46, R50 | 0805 68kΩ-100kΩ | for inverting buffers - values not critical, but the pairs must be matched |

R7, R39 | ||

R1, R2 | ||

R26 | 0805 22kΩ | |

R19 | 0805 <300kΩ | lower value will shorten the time the frequency is temporarily increased during startup |

R32 | 0805 100kΩ | lower value will result in lower startup amplitude |

R24 | 0805 82kΩ | higher value will restrict the frequency range |

R33 | 0805 10Ω | |

R22 | 0805 220kΩ | |

R16 | 0805 100kΩ | frequency CV input impedance |

R17 | 0805 1.5kΩ | |

R18 | 0805 10kΩ | |

R23, R28 | 0805 2.2kΩ | 5% |

R25 | 0805 33kΩ | 5% |

R9, R10 | 0805 68kΩ | 1% |

R11, R14, R15, R27 | 0805 820Ω | 1% |

R12, R13 | 0805 47kΩ | 1% |

R20, R21 | 0805 100kΩ | OTA linearization |

TR1, TR2, TR3, TR4 | THT 100kΩ | calibration trimpots. Vertical multiturn Y or W config |

Z1, Z2 | SOD80 5.1v zener | |

D1, D2 | THT 1n5819 | polarity protection schottky, THT vertical installation recommended |

F1, F2 | 0805 100mA PPTC polyfuse | for example. Will work with 0805 10Ω resistors |

7 LEDs | select R29, R34, R37, R41, R45, R49, R53 according to the LED brightness | |

8 jacks | mono 3.5mm PJ302M | 7 of them with the switch/normalisation pin removed |

1 potentiometer | right angled Alpha 9mm 100kΩ linear | Thonk, the closer to 100kΩ the better the frequency range |

- Adjust TR1 to obtain +-5V (10Vpp) amplitude on the first output (COS 0°)
- Adjust TR4 to obtain +-5V (10Vpp) amplitude on the third output (SIN 90°)
- Adjust TR2 to obtain a nice +-5V (10Vpp) sine-like waveform on the sixth output (225°)
- Adjust TR3 to obtain a nice +-5V (10Vpp) sine-like waveform on the fourth output (135°)

Yusynth quadrature LFO core: outputs a +-8.33V cosine and sine (90° phase shift).
Additionally a small current is supplied to the OTA linearizing diode bias inputs, significantly improving the sine waveshape.

With **C9** = **C11** = 470nF, **R12** = **R13** = 47kΩ, and **R20** = **R21** = 100kΩ the frequency range is 19Hz - 0.0008Hz (20min).
The frequencies can be increased by decreasing C9, C11 or decreasing R12, R13 or increasing R20, R21 (ie. decreasing the OTA linearization current).
The frequency range can also slightly vary depending on the power source and how close the potentiometer is to 100kΩ.
Component changes might result in slightly different amplitudes (can be corrected by calibration with the four trimpots) or even oscillation stability issues.

The core circuit by itself takes several cycles to start oscillating and settle on a stable amplitude,
at very low frequencies it might take even hours.
This sub-circuit temporarily increases the frequency for a couple of seconds (by supplying more current to the
OTA amp bias input) so that the amplitude settles
much quicker (typically under 13 seconds with the help of another amplitude startup circuit).

**C13** (10µF) and **R19** regulate how long the transistor **T1** will be opened to increase the oscillation frequency.
The duration of increased frequency can be shortened by decreasing the C13 capacitance or decreasing the resistance of R19.

Normally the core circuit would start from zero amplitude and slowly build up until it would settle on the stable final amplitude.
This sub-circuit attempts to charge one of the main core capacitors during the first couple of microseconds after powerup,
boosting the amplitude so that the startup is faster. This boosting is not very precise because it depends on how the power
source behaves during this short time.

**R33** (10Ω) limits the charging current, the larger the resistance, the slower the first integrator feedback capacitor **C9** (470nF) will charge.
**R32** (100kΩ) and **C20** (100nF) regulate how long the transistor **T4** will be opened = how long C9 will be allowed to charge.
More charging time or more charging current will result in higher startup amplitude.

startup behavior with this sub-circuit:

startup behavior without this sub-circuit:

continued with 10x lower time resolution:

By adding the SIN + COS signals
we get another SIN signal phase-shifted by PI/4 (45°). This summing circuit is also an inverting buffer, so the result is
additionally phase-shifted by another 180° The summed output signal is stronger by a factor of sqrt(2), so the trimpot should be used to dial
a desired resulting amplitude (around 48kΩ when two 68kΩ summing resistors are used).
The closer the input signals are to sine and cosine waveforms, the closer the output summed signal waveform will resemble the shape of the input waveforms.
If the input signals are slightly distorted, the output summed waveform will look different from the inputs.